Develop a comprehensive test plan, complete test-bench, and robust verification environment including interface agents and Scoreboard in UVM.

Possess deep knowledge of at least one

industry-standard protocol such as Ethernet, PCIe, DDR, USB, CHI/CMN-700, NVMe, or similar.

Strong debugging skills to address test-bench issues quickly and test failures.

Take responsibility for verification closure by addressing Coverage and managing bug reports.

Proficiency in using industry-standard verification tools such as Questasim, VCS, Verdi,or ModelSim

Experience with scripting languages like Python, Perl, or TCL for automation tasks.

Demonstrate a deep understanding of the complete functional verification cycle.

Must have successfully executed at least 2 to 3 SoC/ ASIC/IP Verification projects.

Understand the dynamic nature of customer environments and be able to adapt to runtime changes in schedule, design, etc.

Show strong leadership skills with experience leading projects as a lead and managing a team of at least 3-5 engineers.