Contribute to the definition and document digital subsystem architecture, optimizing for area, power and performance.
Describe modules of the digital subsystem using Verilog or System Verilog HDL.
Plan and execute metric-driven functional verification using System Verilog testbenches. If applicable, UVM can be used.
Perform code linting, logic synthesis applying testability and power reduction techniques, logic equivalence checks, back-annotated static timing analysis, power analysis.
Apply Design for Test (DFT) techniques, perform internal scan chain insertion, Automatic Test Patterns Generation (ATPG), plan functional test vectors if needed.
Coordinate with the Physical Implementation Team for digital floorplan optimization
Contribute and support silicon validation and debug.
Optimize design procedures speed up with self-developed or existing scripts in a script language (ex: Python, PERL, TCL/Tk, shell or similar)
Constantly pursue self-development in areas of weakness and/or design technology updates
Minimum Requirements:
·MS Degree in electrical engineering or equivalent
·4+ years of experience in digital IC circuit design
·Familiarity with Unix OS, scripting languages, Text editors and/or IDE for RTL development
·Familiarity with Cadence Front-End EDA tools
·Knowledge of Backend EDA tools and notions of DSP are preferred
·Good English speaking/reading/writing skills
To apply, please send your resume/CV to HR@orcasemi.com stating the job title you are interested in.
