• BTech/BE in ECE/EEE or related fields with minimum 7.0/10.0 CGPA
• MTech/ME in VLSI/Micro-electronics with minimum 6.5/10.0 CGPA (preferred)
• Strong understanding on digital circuits designs
• Strong understanding in RTL design tools and methodologies
• 10 to 15 years of experience in complex/timing critical RTL designs
• Experience in handling of clock domains, reset domain crossing and low power designs
• Experience in ASIC/FPGA design tools and methodologies
• Experience in on-chip interconnect protocols (AXI 3/4, NoC etc..)
• Experience on standard interface protocol (DDR/HBM/PCIe/CXL etc..)
• Quick learner on new technologies and quickly adapt to changes
• Interact and collaborate within team and customers
• Collaborate with other teams based on the requirements
• Proactive and self-driven approaches to complete tasks
• Experience in managing a small team

Key Responsibilities

• Understand protocol specification from all perspectives
• Define design specification and requirements independently
• Ownership of digital IP and its delivery schedules
• Drive RTL implementation of the modules by considering area/power aspects of digital circuits
• Work with verification team on verifying functionalities and meet coverage metrics
• Timing/Area analysis and closure of IP and/or SoCs
• Performance simulations and optimisations
• Work with other functional teams in integration, qualification of the IP, demonstration of functionalities etc..
• Support management on demand with required data
• Mentor and manage a team of approx. 10 members and plan/review/drive individual tasks

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