Job Responsibilities:
 

• In cooperation with project team develop full chip layout from floor plan to tape out
• Work closely with designers to optimize block performance and area
• Run physical verification on blocks and full chip (LVS, DRC, parasitic extraction...)
• Generate detailed layout schedule and track progress
• Mentor and supervise junior layout designers

Minimum Requirements:
 

• Bachelor's Degree in electrical engineering or equivalent
• 10+ years of experience in analog IC Layout
• Strong experience with Cadence layout tools
• Proven track record of successful completion of multiple full chip tape out
• Knowledge of semiconductor device physics, cross-section, and construction
• Good English speaking/reading/writing skills

To apply, please send your resume/CV to HR@orcasemi.com stating the job title you are interested in.