Experience : 9 Years

Education : B.E, M.E, M.Tech, B.Tech

Role :

Sound knowledge of RTL frond end design principles.

Excellent command over HDL Verilog/VHDL.

Sound knowledge of FPGA design principles. Working with Xilinx/Altera FPGA is preferable..

Must have done RTL synthesis, constraints design, timing closure, RTL designs having CDC.

Must have written test benches to verify the RTL design.

Must have used the RTL development and debugging tools for FPGA (e.g. vivado for Xilinx).

Must have implemented at least a few communication signal processing blocks in RTL (e.g. FFT/IFFT, AGC, Channel Estimation/Equalization, DPD, CFR, Turbo Enoder/Decoder).

Job Description :

Must have good understanding of PHY Layer of at least one OFDM based wireless technology (e.g. 5G/LTE/ WiFi/WiMAX). LTE experience is preferable.

Must know where to use FIFO or RAM in the design. Must have used FIFOs/RAM in the design.

Should know how to write configurable RTL.

Should have used CPRI/OBSA IPs to interface with the RF unit in a wireless communication system.

Understanding of RF fundamentals, RF components, RF chain and it’s working is advantageous.

Ability to learn quickly in a highly dynamic work environment.