Description

• Knowledge of digital design, product quality, and product yield required.
• Defining DFT architecture including scan architecture and MBIST and repair architecture.
• Knowledge of latest DFT techniques including compression necessary.
• Knowledge of SSN architecture.
• Test point insertion and deep coverage analysis including defect coverage required.
• Ability to interface with RTL/Timing/PD/packaging and other teams is required.
• Pattern delivery to Test engineering, Experience will silicon bring up of Scan/JTAG/MBIST needed.
• Knowledge of post silicon process including HTOL/burn-in necessary

What you’ll bring

• Strong analytical skills
• Experience in physical design methodology development or worked as SoC physical design lead owning top-level.
• Hierarchical push down and delivered blocks/partitions to block PD
• Preferred – power distribution, static timing analysis and physical design verification
• Worked with library characterization team – preferred
• Worked with foundry for rule deck development – preferred
• Good at TCL/Perl/Make file scripting
• Familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process
• Experience in tool set such as Cadence Genus, Cadence Innovus, Mentor Calibre is an advantage

Education & Experience

• BE / BTech / ME / MTech in ECE/CSE with 8+ years of experience

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