Job Description 

The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Design/verify the RTL code for the high speed SerDes related digital blocks • Excellent verbal and written communication skills are required. • Experience in synthesis of complex SoCs block/top level and writing timing constraints. • Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints. • Experience in post-layout STA closure and timing ECOs • Excellent problem solving and debug skills • Worked in technology nodes 45nm and below. • Knowledge of low-power aware implementation is a plus

 Mandatory Skills

 Timing Closure, STA, ECOs, Synthesis, SDC

 Education Qualification 

BE/B.Tech in VLSI/ECE. 

5+ years of experience in verification of analog mixed signal blocks.

 Hands on tool expertise Tools: cadence AMS

 tools and proficiency in Verilog, verilogA and VAMS languages

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