• Develops timing constraints bottom-up for blocks and top-level.
• Adopt the methodology suitable to complexity and nature of the designs.
• Drive multiple iterations/regressions to help in managerial decision making.
• Works for optimal use of computing systems and timing sign-off tools across tapeouts.

What you’ll bring

• Strong analytical and scripting skills
• Experience in timing sign-off methodology development or worked as SoC physical design lead owning top-level.
• Preferred – experience with timing sign-off using POCV/SOCV and AOCV.
• Worked with library characterization team – optional
• Worked with clock tree team / have experience in clock mesh simulations – optional
• Good at TCL/Perl/Makefile scripting knowledge.
• Experience in Tempus, PrimeTime or both.
• Exposure to major industry tool flows of Synopsys/Cadence/Siemens

Education & Experience

• BE / BTech / ME / MTech in ECE/CSE with 8+ years of experience

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