JOB DESCRIPTION

• 12+ Years of Digital Verification experience.
• Ability to manage multiple teams
• Should have been part of End-to-End Verification Cycle.
• Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies
• Experience with RTL concepts
• Experience with AHB/AXI protocol
• Expertise in multiple Standard protocols (Ex: PCI-e/USB/Ethernet/CPU )
• Knowledge of Perl/Python is Must
• Develop IP level/SoC level test plans based on the design/architectural specs.
• Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level
• Coverage Analysis , debug test failures to identify test case issues and RTL design issues
• Develop block/full chip level verification environment and its components
• Expertise to Testplan, testcase, functional coverage and assertions with hands-on experience.

Skills & Experience

• SoC / IP Verification
• SystemVerilog
• SystemVerilog Assertions
• Universal Verification Methodology (UVM)
• C
• Python / Perl 

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